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NTE3880 Integrated Circuit NMOS, 8-Bit Microprocessor (MPU), 4MHz
Description: The NTE3880 is a third generation single chip microprocessor with unrivaled computational power. This increased computational power results in higher system through-put and more efficient memory utilization when compared to second generation microprocessors. In addition it is very easy to implement into a system because of it's single voltage requirement plus all output signals are fully decoded and timed to control standard memory or peripheral circuits. The circuit is implemented using an N- channel, ion implanted, silicon gate MOS process. This device has an internal register configuration which contains 208 bits of Read/Write memory that are accessible to the programmer. The registers include two sets of six general purpose registers that may be used individually as 8-bit registers or as 16-bit register pairs. There are also two sets of accumulator and flag registers. The programmer has access to either set of main or alternate registers through a group of exchange instructions. This alternate set allows foreground/background mode of operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16-bit stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine nesting and simplification of many types of data handling. The two 16-bit index registers allow tabular data manipulation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transparent refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits of the pointer. An indirect call is then made to this service address. Features: D Single Chip, N-Channel Silicon Gate D 158 Instructions - Includes all 78 of the 8080A Instructions with Total Software Compatibility. New Instructions Include 4-, 8- and 16-Bit Operations with more useful Addressing Modes such as Indexed, Bit and Relative D 17 Internal Registers D Three Modes of Fast Interrupt Response plus a Non-Maskable Interrupt D Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic D 1.0s Instruction Execution Speed D Single 5VDC Supply and Single-Phase 5V Clock D Out-Performs any other Single-Phase 5V Clock D All Pins TTL Compatible D Built-In Dynamic RAM Refresh Circuitry
Absolute Maximum Ratings: Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Note 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics: (TA = 0 to 70C, VCC = 5V 5% unless otherwise specified)
Parameter Clock Input Low Voltage Clock Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current Input Leakage Current Tri-State Output Leakage Current in Float Tri-State Output Leakage Current in Float Data Bus Leakage Current in Input Mode Symbol VILC VIHC VIL VIH VOL VOH ICC IL1 ILOH ILOL ILD VIN = 0 to VCC VOUT = 2.4 to VCC VOUT = 0.4V 0 VIN VCC IOL = 1.8mA IOH = -250A Test Conditions Min -0.3 VCC-0.6 -0.3 2.0 - 2.4 - - - - - Typ - - - - - - 90 - - - - Max 0.80 VCC+3 0.8 VCC 0.4 - 200 10 10 -10 10 Unit V V V V V V mA A A A A
Capacitance: (TA = +25C, f = 1MHz, unmeasured pins to GND unless otherwise specified)
Parameter Clock Capacitance Input Capacitance Output Capacitance Symbol C CIN COUT Test Conditions Min - - - Typ - - - Max 35 5 10 Unit pF pF pF
AC Characteristics: (TA = 0C to +70C, VCC = +15V 5% unless otherwise specified)
Parameter Clock Period Clock Pulse Width, Clock High Clock Pulse Width, Clock Low Clock Rise and Fall Time Address Output Delay Data to Float Address Stable Prior to MRFQ (Memory Cycle) Address Stable Prior to IOFQ, RD or WR (I/O Cycle) Address Stable from RD, WR, IORQ, or MREQ Address Stable from RD or WR During Float Symbol Signal Test Conditions tc tw (H) tw (L) tr, tf tD (AD) tF (AD) tacm taci tca tcaf A0-15 CL = 50pF Min 25 110 110 - - - Note 4 Note 5 Note 6 Note 7 Typ - - - - - - - - - - Max Note 2 Note 3 2000 30 110 90 - - - - Unit s ns ns ns ns ns ns ns ns ns
Note Note Note Note Note Note
2. 3. 4. 5. 6. 7.
tc = tw (H) + tw (L) + tr + tf. Although static by design, testing guarantees tw (H) of 200s maximum. tacm = tw (H) + tf-65. taci = tc-70. tca = tw (L) + tr-50. tcaf = tw (L) + tr-45.
AC Characteristics (Cont'd): (TA = 0C to +70C, VCC = +15V 5% unless otherwise specified)
Parameter Data Output Delay Delay to Float During Write Cycle Data Setup Time to Rising Edge of Clock During M1 Cycle Data Setup Time to falling Edge of Clock During M2 to M5 Data Stable Prior to WR (Memory Cycle) Data Stable Prior to WR (I/O Cycle) Data Stable From WR Any Hold Time for Setup Time MREQ Delay From Falling Edge of Clock, MREQ Low MREQ Delay From Rising Edge of Clock, MREQ High MREQ Delay From Falling Edge of Clock, MREQ High Pulse Width, MREQ Low Pulse Width, MREQ High IORQ Delay From Rising Edge of Clock IORQ Low IORQ Delay From Falling Edge of Clock IORQ Low IORQ Delay From Rising Edge of Clock IORQ High IORQ Delay From Falling Edge of Clock IORQ High RD Delay From Rising Edge of Clock, RD Low RD Delay From Falling Edge of Clock, RD Low RD Delay From Rising Edge of Clock, RD High RD Delay From Falling Edge of Clock, RD High WR Delay From Rising Edge of Clock, WR Low WR Delay From Falling Edge of Clock, WR Low WR Delay From Falling Edge of Clock, WR High Pulse Width, WR Low tDH (WR) tw (WRL) tDL (WR) WR CL = 50pF tDH (RD) tDL (RD) RD CL = 50pF tDH (IR) tw (MRL) tw (MRH) tDL (IR) IORQ CL = 50pF tdcm tdci tcdf tH tDL (MR) tDH (MR) MREQ CL = 50pF Symbol tD (D) tF (D) tS (D) Signal D0-7 Test Conditions CL = 50pF Min - - 35 50 Note 8 Note 9 Note 10 - - - - Note 11 Note 12 - - - - - - - - - - - Note 13 Typ - - - - - - - - - - - - - - - - - - - - - - - - - Max 150 90 - - - - - 0 85 85 85 - - 75 85 85 85 85 95 85 85 65 80 80 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 8. Note 9. Note10. Note 11. Note12. Note13.
tdcm = tc-170. tdci = tw (L) + tr-170. tcdf = tw (L) + tr-70. tw (MRL) = tc-30. tw (MRH) = tw (H) + tr-20. tw (WRL) = tc-30.
AC Characteristics (Cont'd): (TA = 0C to +70C, VCC = +15V 5% unless otherwise specified)
Parameter M1 Delay From Rising Edge of Clock, M1 Low M1 Delay From Rising Edge of Clock, M1 High RFSH Delay From Rising Edge of Clock, RFSH Low RFSH Delay From Rising Edge of Clock, RFSH High WAIT Setup Time to Falling Edge of Clock HALT Delay Time From Falling Edge of Clock INT Setup Time to Rising Edge of Clock Pulse Width, NM1 Low BUSRQ Setup Time to Rising Edge of Clock BUSAK Delay From Rising Edge of Clock, BUSAK Low BUSAK Delay From Rising Edge of Clock, BUSAK High RESET Setup Time to Rising Edge of Clock Delay to Float (MREQ, IORQ, RD and WR) M1 Stable Prior to IORQ (Interrupt Ack.) Symbol tDL (M1) tDH (M1) tDL (RF) tDH (RF) ts (WT) tD (HT) ts (IT) tw (NML) ts (BQ) tDL (BA) tDH (BA) ts (RS) tF (C) tmr RESET WAIT HALT INT NM1 BUSRQ BUSAK CL = 50pF CL = 50pF RFSH CL = 50pF Signal M1 Test Conditions CL = 50pF Min - - - - 70 - 80 80 50 - - 60 - Note 14 Typ - - - - - - - - - - - - - - Max 100 100 130 120 - 300 - - - 100 100 - 80 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note14. tmr = 2tc + tw (H) + tf-65. Note15. Data should be enabled onto the CPU data bus when RD is active. During interrupt acknowledge data should be enabled when M1 and IORQ are both active. Note16. All control signals are internally synchronized, so they may be totally asynchronous with respect to the clock. Note17. The RESET signal must be active for a minimum of 3 clock cycles. Note18. Output Delay vs. Loaded Capacitance VCC = 5V 5% TA = +70C Add 10ns delay for each 50pf increase in load up to maximum of 200pF for data bus and 100pF for address & control lines.
Pin Connection Diagram 40 A10 A11 1 39 A9 A12 2 38 A8 A13 3 A14 4 37 A7 A15 5 36 A6 System Clock Input 6 35 A5 34 A4 D4 7 33 A3 D3 8 D5 9 32 A2 D6 10 31 A1 30 A0 (+) 5V 11 29 GND D2 12 D7 13 28 RFSH 27 M1 D0 14 D1 15 26 RESET 25 BUSRQ INT 16 NMI 17 24 WAIT HALT 18 23 BUSAK MREQ 19 22 WD IORQ 20 21 RD
40
21
1 2.055 (52.2)
20 .550 (13.9) Max .155 (3.9)
.100 (2.54)
.019 (0.5)
.137 (3.5)
.650 (16.5)

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